Sigma-delta analog-to-digital converter circuit with real time correction for digital-to-analog converter mismatch error

ABSTRACT

An estimate of unit current element mismatch error in a digital to analog converter circuit is obtained through a correlation process. Unit current elements of the digital to analog converter circuit are actuated by bits of a thermometer coded signal generated in response to a quantization output signal. A correlation circuit generates the estimates of the unit current element mismatch error from a correlation of a first signal derived from the thermometer coded signal and a second signal derived from the quantization output signal.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority from United States Provisional Application for Patent No. 63/020,256 filed May 5, 2020, the disclosure of which is incorporated by reference.

TECHNICAL FIELD

Embodiments generally relate to an analog-to-digital converter circuit and, in particular, to a sigma-delta analog-to-digital converter circuit.

BACKGROUND

FIG. 1 shows a time domain block diagram of a conventional sigma-delta analog-to-digital converter circuit 10. The circuit 10 includes a first order sigma-delta modulator circuit 12 having an input configured to receive an analog input signal A and an output configured to generate a digital output signal B comprised of a pulse density modulated pulse stream of 1-bit codes. The ratio formed by a count of the number of pulses in the pulse stream of the signal B divided by a total number of samples (set by a sampling rate fs) of the input signal A over a known time interval represents the instantaneous magnitude of the input signal A. The circuit 10 further includes a decimator circuit 14 that accumulates and averages the pulses in the pulse stream of the digital output signal B to generate a digital signal C comprised of a stream of multi-bit (M-bit, where M>>1) digital words at a data rate set by a decimation rate fd, where fd<<fs (referred to in the art as oversampling).

The first order sigma-delta modulator circuit 12 comprises a difference amplifier 20 (or summation circuit) having a first (non-inverting) input that receives the analog input signal A and a second (inverting) input that receives an analog feedback signal D. The difference amplifier 20 outputs an analog difference signal vdif in response to a difference between the analog input signal A and the analog feedback signal D (i.e., vdif(t)=A(t)−D(t)). The analog difference signal vdif is integrated by an integrator circuit 22 to generate a change signal vc having a slope and magnitude that is dependent on the sign and magnitude of the analog difference signal vdif. A voltage comparator circuit 24 samples the change signal vc at the sampling rate fs and compares each sample of the change signal vc to a reference signal vref to generate a corresponding the single bit pulse of the digital output signal B (where the single bit has a first logic state if vc≥vref and has a second logic state if vc<vref). The voltage comparator circuit 24 effectively operates as a single bit quantization circuit. A single bit digital-to-analog converter (DAC) circuit 26 then converts the logic state of the digital output signal B to a corresponding analog voltage level for the analog feedback signal D.

It is possible to instead implement the sigma-delta modulator circuit 12 with a multi-bit quantization (for example, N bits, where 1<N<<M) as shown by FIG. 2. This circuit implementation requires an N-bit quantization circuit 24′ and an N-bit DAC circuit 26′ in the feedback loop. The quantization circuit 24′ samples the change signal vc at the sampling rate fs and generates for each sample a corresponding N-bit code word for the digital output signal B. The DAC circuit 26′ converts the N-bit code word of the digital output signal B to a corresponding analog voltage level for the analog feedback signal D. The decimator circuit 14 accumulates and averages the N-bit code words in the stream of the digital output signal B to generate a digital signal C comprised of the stream of multi-bit (M-bit, where M>>N) digital words at a data rate set by a decimation rate fd. In an example, N=3 to 5 bits and M=12 to 16 bits. The use of multi-bit quantization presents a number of advantages including: permitting operation of the modulator to achieve a given resolution using a lower sampling rate fs; or permitting operation of the modulator to achieve a higher resolution for a given sampling rate fs.

A key characteristic of the sigma-delta modulator circuit 12 is its ability to push the quantization noise due to operation of the quantization circuit 24, 24′ to higher frequencies away from the signal of interest. This is known in the art as noise shaping. The decimator circuit 14 can then be implemented with a low-pass filtering characteristic to substantially remove the high frequency components of the shaped quantization noise.

The output (digital signal B, also referred to herein as v(k)) of the sigma-delta analog-to-digital converter circuit using an ideal DAC circuit 26′ is given by the following equation:

v(k)=u(k)·stf(k)+q(k)·ntf(k)

where: k is time, u(k) is the input signal A, q(k) is the quantization error introduced by the quantization circuit 24′, stf(k) is impulse response of the signal transfer function of the system and ntf(k) is the impulse response of the noise transfer function of the system.

The logical structure of the DAC circuit 26′ can be viewed as N unit current sources where each unit current element I_(u) of the DAC circuit 26′ is controlled by one bit of a selecting signal b_(i)(k) that is generated in response to the digital output signal B. So, for the DAC circuit 26′ to have N+1 output levels, N unit current sources are needed. Each unit current element I_(u) is controlled by one of the bits b_(i)(k), where i=1, 2, . . . , N designates the particular unit current element being controlled.

Each unit current source is configured to output a current having a same nominal value. In reality, however, the same nominal value for the current generated by the unit current sources of the DAC circuit 26′ cannot be achieved. The multibit DAC circuit 26′ is inherently non-linear (as compared to the single bit DAC circuit 26 of FIG. 1) because of static element mismatch arising from process, voltage and temperature variation. In such a non-ideal multibit DAC circuit 26′, an error e_(i) is introduced by the i^(th) unit current element I_(u) to the ideal b_(i)(k) value. The effect of this error manifests as a part of the ADC output v(k) for digital signal B as follows:

v(k)=u(k)·stf(k)+q(k)·ntf(k)+Σ_(i=1) ^(N) e _(i) ·b _(i)(k)·etf(k)

where: the term Σ_(i=1) ^(N)e_(i)·b_(i)(k)·etf(k) is introduced due to DAC static element mismatch and can be referred to herein as the DAC error, and etf(k) is the impulse response of the error transfer function. The static element mismatch of the multibit DAC circuit 26′ along with the integral non-linearity results in spurs appearing at output, and this will seriously degrade the performance of the sigma-delta analog-to-digital converter circuit.

In the case where the N-bit code word for the digital output signal B is thermometer coded, the static element mismatch across the thermometric unit current elements I_(u) controlled by the thermometer coded selecting signal b_(i)(k) is the primary concern. For a thermometer coded signal, it is noted that there is a fixed pattern on the selection of unit current elements I_(u) for the N possible codes. The selecting signals b_(i)(k) are strongly correlated to the DAC input and as the signal b_(i)(k) is a scaled version of the ADC output signal v(k) it will contain a component of the input signal. As a result, input signal-dependent tones will appear at the ADC output. To solve this issue, a decorrelation of the thermometer coded selecting signals b_(i)(k) at the DAC input is necessary.

A solution for providing this decorrelation of the thermometer coded selecting signals b_(i)(k) is shown in FIG. 3. The thermometer coded selecting signals b_(i)(k) generated in response to the ADC output signal v(k) are randomly scrambled by a scrambler data weighted averaging (DWA) circuit 28. The scrambler DWA circuit 28 reorders the N bits in the thermometer code of the selecting signal b_(i)(k) in a random manner without altering the absolute value of those bits (for example, thermometer coded bits <1,1,1,1,0,0,0,0> can be randomly reordered to <1,0,0,1,0,0,1,1> with no change in the absolute value of 4). Because of this, the selection of unit current elements I_(u) at each time k in the multibit DAC circuit 26′ becomes dynamic or random. This zero-order randomization is a dynamic element matching DEM technique achieved through a digital rearranging process implemented by the scrambler DWA circuit 28. The selecting signals b_(i)(k) are now decorrelated with the DAC input signal 30, eliminating the input signal dependent tones at the DAC output.

The output of the ideal DAC is the sum of the outputs of the unit current elements I_(u):

a _(ideal)(k)=ΔΣ_(i=1) ^(N) b _(i)(k)

wherein: Δ equals the quantization step.

In practice, the current sources used in the DAC are not ideal in nature resulting in deviations from their ideal value. Assume e_(i) (i=1, 2, . . . , N) are the values of normalized deviations of the unit elements outputs from their mean value (referred to as unit element errors). Thus, the output of each unit element can be represented as Δ (1+e_(i)). The output of a non-ideal (actual) DAC is then:

a _(actual)(k)=ΔΣ_(i=1) ^(N) b _(i)(k)+ΔΣ_(i=1) ^(N) b _(i)(k)·e _(i)

The second term of the foregoing equation is the error introduced in the DAC and is referred as DAC error (or mismatch error). This DAC error is basically the selecting signals b_(i)(k) multiplied by the corresponding normalized deviations e_(i) over N signals:

DAC error=ΔΣ_(i=1) ^(N) b _(i)(k)·e _(i)

The DAC error appears in the output equation of the sigma-delta analog-to-digital converter circuit after passing through the signal transfer function (STF(z)) of the ADC with a phase shift of 180°. Thus, the error transfer function (ETF(z)) for the DAC can be defined in the slowest feedback path as follows:

ETF(z)=−STF(z)

So, the DAC error at the output of the ADC is given by:

Σ_(i=1) ^(N) b _(i)(k)·e _(i) ·etf(k)

It will be noted here that the Δ of the equation is canceled by the Δ of the quantizer before appearing at the ADC output.

As a result of the non-linearity introduced in the analog output of the DAC by the DAC error, a distorted modulator output is produced. The non-linearity also modulates the quantization noise of the quantization circuit 24′ into the signal band resulting in a degraded signal-to-noise ratio (SNR).

In order to take advantage of the benefits of multi-bit quantization in sigma-delta modulator circuits, it is necessary to estimate the inherent non-linearity (i.e., DAC error) present in the operation of the multi-bit DAC circuit and apply a correction to nullify its effects.

SUMMARY

For sigma-delta analog to digital converters (ADCs) that utilize a feedback digital to analog converter (DAC) for conversion, the final analog output of the DAC can be affected or distorted by non-linearity error in the DAC due to DAC element mismatch. A digital process performs an estimation to determine the DAC element mismatch error. Digital codes at the quantizer output are convolved with a loop error transfer function and the subsequent ADC outputs are filtered and correlated with a modified form of the convolved digital codes to estimate the DAC element mismatch error.

In an embodiment, a circuit for estimating unit current element mismatch error in a digital to analog converter circuit, where unit current elements of the digital to analog converter circuit are actuated by bits of a thermometer coded signal generated in response to a quantization output signal, comprises: a correlation circuit configured to generate estimates of the unit current element mismatch error from a correlation of a first signal derived from the thermometer coded signal and a second signal derived from the quantization output signal.

In an embodiment, a system comprises: a quantization circuit configured to generate a quantization output signal; a digital to analog converter (DAC) circuit including unit current elements that are actuated by bits of a thermometer coded signal generated in response to the quantization output signal; and an error estimation circuit configured to estimate unit current element mismatch error in the digital to analog converter circuit. The error estimation circuit comprises: a correlation circuit configured to generate the estimates of the unit current element mismatch error from a correlation of a first signal derived from the thermometer coded signal and a second signal derived from the quantization output signal.

In an embodiment, a sigma-delta modulator comprises: a differencing circuit having a first input configured to receive an input signal and a second input configured to receive a feedback signal and an output configured to generate a difference signal; a loop filter circuit configured to filter the difference signal and generate a change signal; a quantization circuit configured to sample the change signal at a sampling frequency rate, quantize the sampled change signal and generate a stream of code words; a digital-to-analog converter (DAC) circuit configured to generate the feedback signal by converting a thermometer coded signal generated in response to the stream of code words, wherein the DAC circuit has a non-ideal operation due to mismatch error; a replica DAC circuit that provides a digital replication of the DAC circuit, said digital replication comprising estimated error programming which accounts for the non-ideal operation of the DAC circuit due to mismatch error; and an error estimation circuit configured to generate the estimated error programming from a correlation of the thermometer coded signal and the stream of code words.

BRIEF DESCRIPTION OF THE DRAWINGS

For a better understanding of the embodiments, reference will now be made by way of example only to the accompanying figures in which:

FIG. 1 is a block diagram of a conventional sigma-delta analog-to-digital converter circuit with single bit quantization;

FIG. 2 is a block diagram of a conventional sigma-delta analog-to-digital converter circuit with multi-bit quantization;

FIG. 3 is a block diagram of a conventional sigma-delta analog-to-digital converter circuit with multi-bit quantization and scrambling of DAC codes;

FIG. 4 is a block diagram of a sigma-delta analog-to-digital converter circuit with multi-bit quantization and feedback digital-to-analog converter mismatch correction; and

FIG. 5 is a block diagram for an error estimation circuit.

DETAILED DESCRIPTION

Reference is now made to FIG. 4 which shows a block diagram of a sigma-delta analog-to-digital converter circuit 110 with multi-bit quantization and feedback digital-to-analog converter (DAC) mismatch correction. The circuit 110 includes an N-bit sigma-delta modulator circuit 112 having an input configured to receive an analog input signal A and an output configured to generate a digital output signal B comprised of a stream of N-bit code words. The sigma-delta modulator circuit 112 comprises a difference amplifier 120 (i.e., summation circuit) having a first (non-inverting) input that receives the analog input signal A and a second (inverting) input that receives an analog feedback signal D. The difference amplifier 20 outputs an analog difference signal vdif in response to a difference between the analog input signal A and the analog feedback signal D (where vdif(t)=A(t)−D(t)). The analog difference signal vdif is integrated by a K-order loop filter 116 (using, for example, K integrator circuits 122) to generate a change signal vc having a slope and magnitude that is dependent on the sign and magnitude of the analog difference signal vdif. An N-bit quantization circuit 124 samples the change signal vc at the sampling rate fs and generates for each sample a corresponding N-bit code word of the digital output signal B (also referred to as the ADC output v(k)). This signal is thermometer coded with the bits of the code word scrambled by a data weighted averaging (DWA) scrambler circuit 128 to generate a selecting signal b_(i)(k). An N-bit digital-to-analog converter (DAC) circuit 126 in the feedback loop converts the bits of the scrambled thermometer coded selecting signal b_(i)(k) to generate a corresponding voltage level for the analog feedback signal D.

The sigma-delta modulator circuit 112 implements a loop filter 116 with a K-order integration circuit implementation. In the illustration of FIG. 1, K=1 as there is only one integration shown (with integrator 122) in the loop filter 116, but it will be understood that this is by way of example only, and K may equal 2, 3 or more as needed by the desired noise shaping and circuit application. Those skilled in the art know how to implement a K>1 order loop filter 116 for the sigma-delta modulator circuit 112.

The stream of N-bit code words for the digital output signal B produced by the N-bit quantization circuit 124 are input to the scrambling circuit 128 to be passed through, after scrambling, to the N-bit DAC circuit 126 in the feedback path. This stream of N-bit code words for the digital output signal B is further input to a replica DAC circuit 118. In this context, the replica DAC circuit 118 is programmed by an error estimation circuit 140 to digitally model the operation of the feedback N-bit DAC circuit 126. In other words, to digitally model the ideal DAC operation plus the DAC error introduced by the non-linear operation of the unit elements. In response to this programming, the replica DAC circuit 118 processes the ADC output v(k) to remove the DAC error.

The replica DAC circuit 118 provides a digital replication of the analog N-bit DAC circuit 126, that replication specifically accounting for the non-ideal operation of the N-bit DAC circuit 126 due to element mismatch. More specifically, the replica DAC circuit 118 is programmed with a plurality of digital code words that are directly proportional to the value of the mismatched unit elements of the analog N-bit DAC circuit 126. In other words, digital codes corresponding to the analog value of the unit element error e_(i). The digital code words can be of any selected precision P, and are determined by the error estimation circuit 140. It will be appreciated that if the digital model provided by the replica DAC circuit 118 is substantially identical to the non-ideal actual operation of the analog N-bit DAC circuit 126, then the digital signal E output from the digital DAC copy circuit 118 will be functionally equivalent to the analog feedback signal D output from the analog N-bit DAC circuit 126. In this context, “functionally equivalent” means that an analog conversion of the digital value for the digital signal E generated in response to signal B by the digital DAC copy circuit 118 is substantially equal to the corresponding analog value for the analog feedback signal D generated in response to that same signal B. The digital signal E output by the digital DAC copy circuit 118 comprises a stream of P-bit code words (where P>N, the higher resolution provided by P bits being necessary to provide fractional components necessary to account for effects of the mismatch error). The difference in bits (P−N) defines the degree of substantial equality that is achievable.

The operation of the replica DAC circuit 118 may be better understood through the use of an example. Assume that the scrambled thermometer coded selecting signal b₁(k) would activate two unit current elements. If the analog N-bit DAC circuit 126 had an ideal functional operation, the analog voltage for the analog feedback signal D output from the analog N-bit DAC circuit 126 would have a value of 2*Δ. However, due to mismatch error, the voltage of the generated analog feedback signal D output from the analog N-bit DAC circuit 126 instead has a value of 2*Δ+e₁Δ+e₂Δ. The error estimation circuit 140 operates to process the scrambled thermometer coded selecting signal b_(i)(k) and the ADC output v(k) to estimate the error e_(i) for each of the unit current elements. The replica DAC circuit 118 is programmed with the estimation of the error e_(i). So, with consideration to the forgoing example, the digital signal E output from the replica DAC circuit 118 will be a code word with a precision of P-bits formed by summing the N-bit digital code for 2*Δ (i.e., the ideal response) plus the digital code for Δ times the sum of the programmed digital code words for the unit element errors e₁ and e₂ (i.e., Δ(e₁+e₂)) which is the introduced mismatch error.

The circuit 110 further includes a decimator circuit 114 that accumulates and averages the P-bit code words in the stream of the digital output signal E to generate a digital signal C comprised of a stream of multi-bit (M-bit) digital words at a data rate set by a decimation rate fd, where fd<<fs and 1<N<P<<M. The decimator circuit 114 implements a low pass filtering to effectively remove the high-passed signal components of the quantization error and mismatch error.

As previously noted, the ADC output v(k) of the sigma-delta analog-to-digital converter circuit consists of:

1) the filtered input signal u′(k) which is equal to u(k)·stf(k), where stf(k) is impulse response of the signal transfer function (STF(z)) of the system;

2) the filtered quantization noise q′(k) which is equal to q(k)·ntf(k), where ntf(k) is the impulse response of the noise transfer function (NTF(z)) of the system; and

3) the filtered DAC error Σ_(i=1) ^(N)b₁′(k)·e_(i), where b_(i)′(k)=b_(i)(k)·etf(k) and etf(k) is the impulse response of the error transfer function (ETF(z)) of the system.

The ADC output v(k) is thus given by the equation:

v(k)=u′(k)+q′(k)+Σ_(i=1) ^(N) b _(i)′(k)·e _(i)

The error estimation circuit 140 receives the scrambled thermometer code word b_(i)(k) output from the data weighted averaging (DWA) scrambler circuit 128 and the digital output signal B (v_(i)(k)) produced by the N-bit quantization circuit 124. These signals are processed to estimate the unit element errors (the estimated errors referred to herein as ê_(i)). The replica DAC circuit 118 is then programmed with these estimated errors ê_(i), and a DAC error correction term:

DAC err corr=Σ_(i=1) ^(N) b _(i)′(k)·ê _(i)

is eliminated from the ADC output v(k) by the replica DAC circuit 118 to substantially cancel the DAC error Σ_(i=1) ^(N)b_(i)′(k)·e_(i) and obtain a corrected ADC output v_(c)(k):

v _(c)(k)=u′(k)+q′(k)

The corrected ADC output v_(c)(k) is then processed through the decimator 114 at the decimation rate fd to generate the digital output signal C.

Reference is now made to FIG. 5 which shows a block diagram for the error estimation circuit 140. In order to identify and formulate a measure that remains constant and is independent of the input thermometer code from the selecting signals, the term n_(i)(k) is defined as:

${n_{i}(k)} = {{b_{i}(k)} - {\frac{1}{N}{\sum_{i = 1}^{N}{b_{i}(k)}}}}$

A summation circuit 160 receives the scrambled thermometer code word b_(i)(k) and calculates the Σ_(i=1) ^(N)b_(i)(k) component and a divider circuit 162 applies the 1/N fraction. The output of the divider circuit 162 is applied to one input of a subtraction circuit 164. Another input of the subtraction circuit 164 receives the scrambled thermometer code word b_(i)(k) signal and performs the subtraction operation to generate the term n_(i)(k).

It can be shown that for all values of b_(i)(k), the sum of n_(i)(k) is zero:

Σ_(i=1) ^(N) n _(i)(k)=0

A determination is now made as to whether the generated term n_(i)(k) has any impact on the actual DAC output and the corresponding ADC output. With reference again to the non-ideal DAC output of:

a _(actual)(k)=ΔΣ_(i=1) ^(N) b _(i)(k)+ΔΣ_(i=1) ^(N) b _(i)(k)·e _(i)

and, since Σ_(i=1) ^(N)e_(i)=0 for a given DAC, then:

a _(actual)(k)=ΔΣ_(i=1) ^(N) b _(i)(k)+ΔΣ_(i=1) ^(N) n _(i)(k)·e _(i)

As a result, the DAC error can be represented as:

DAC error=ΔΣ_(i=1) ^(N) n _(i)(k)·e _(i)

Substituting for the term n_(i)(k), the ADC output can be re-written as:

v(k)=u′(k)+q′(k)+Σ_(i=1) ^(N) n _(i)′(k)·e _(i)

where: u′(k) is the input signal A passed through the modulator STF(z) and q′(k) is the shaped quantization error. A first signal conditioning circuit 168 receives the signal n_(i)(k) and applies a filtering 168 a and a decimation 168 b to generate the signal n_(i)′(k). Filtering is needed to remove the STF passed input signal u′(k) from the modulator output. This is done to de-correlate v(k) with the input signal u(k) because any signal component present in the output will interfere with the correlation operation. In this context, n_(i)′(k) is the STF passed version of n_(i)(k). Recall that n_(i)(k) is injected into the loop (via feedback) at the summation node at the input. So, n_(i)(k) and u(k) both pass through an identical STF and are labeled as n_(i)′(k) and u′(k), respectively. The filtering 168 a has a transfer function that is a combination of error transfer function (ETF(z)) and a high pass filtering. As a result, the overall signal conditioning operation is therefore one of a polyphase decimation filtering.

Since the scrambled thermometer code word b_(i)(k) signal and the input signal u′(k) can be assumed to be decorrelated, the correlation between v(k) and n_(i)′(k) can be computed to obtain an estimate of the errors. The correlation may be mathematically expressed as:

CORR[v(k),n _(i)′(k)]=CORR[u′(k),n _(i)′(k)]+CORR[q′(k),n _(i)′(k)]+CORR{[Σ_(j=1) ^(N) e _(j) ·n _(j)′(k)],n _(i)′(k)}

For every i there are N number of j's where N is the number of DAC elements. Intuitively, the above-expression means that N bit streams (STF passed n_(i)′(k)) emerging from feedback DAC input (because DAC has N inputs) when correlated with the modulator output (which is a summation of applied codes to DAC+DAC error represented by [Σ_(j=1) ^(N)e_(j)·n_(j)′(k)]) provides N outputs that are proportional to the DAC element error). To elaborate further, ‘i’ is the digital part of the equation, where ‘i’ data lines exist as unique physical entities. ‘j’ is the index to represent DAC passed, STF passed, quantizer passed mashed/summed data, where ‘j’ individually is no longer discernable.

The first two terms of the foregoing equation evaluate to zero under the following assumed conditions:

a) e_(i) terms follow a normal distribution and are relatively constant over a period;

b) the input signal u(k) is filtered out from the ADC output; and

c) the quantization error q′(k) is white, uniformly distributed and uncorrelated to n_(i)′(k).

With these assumptions in place, the correlation may be simplified and mathematically expressed as:

CORR[v′(k),n _(i)′(k)]=e _(i)+{Σ_(j=1,j≠i) ^(N) e _(j)(k)·CORR[n _(j)′(k),n _(i)′(k)]}

where: v′(k) is the ADC output filtered so that it does not contain the input signal. The error estimation circuit 140 accordingly includes a second signal conditioning circuit 172 that receives the signal v(k) as output from the quantizer and applies a high pass filtering (HPF, reference 172 a) and a decimation 172 b function to produce the signal v′(k). The overall signal conditioning operation is therefore one of a polyphase decimation high pass filtering.

It will be noted at this point that the signal b_(i)(k) branches out of the scrambler 128 into the following two paths:

a) for v_(i)′(k): the path comprises a DAC, the STF, and the quantizer followed by a polyphase decimation high pass filter (using the second signal conditioning circuit 172); and

b) for n_(i)′(k): the path comprises a digital approximation of the STF and a polyphase decimation high pass filtering (using the first signal conditioning circuit 168).

A correlation circuit 180 performs the correlation CORR[v′(k),n_(i)′(k)]. This correlation operation produces a matrix of size N×1 as follows:

$\begin{bmatrix} {{CORR}\left\lbrack {{v^{\prime}(k)},{n_{1}^{\prime}(k)}} \right\rbrack} \\ {{CORR}\left\lbrack {{v^{\prime}(k)},{n_{2}^{\prime}(k)}} \right\rbrack} \\ \vdots \\ {{CORR}\left\lbrack {{{v'}(k)},{n_{N}^{\prime}(k)}} \right\rbrack} \end{bmatrix} = {R \cdot \begin{bmatrix} e_{1} \\ e_{2} \\ \vdots \\ e_{N} \end{bmatrix}}$ where: $R = \begin{bmatrix} 1 & \ldots & {{CORR}\left\lbrack {{n_{N}^{\prime}(k)},{n_{1}^{\prime}(k)}} \right\rbrack} \\ {{CORR}\left\lbrack {{n_{1}^{\prime}(k)},{n_{2}^{\prime}(k)}} \right\rbrack} & \ldots & {{CORR}\left\lbrack {{n_{N}^{\prime}(k)},{n_{2}^{\prime}(k)}} \right\rbrack} \\ \vdots & \ddots & \vdots \\ {{CORR}\left\lbrack {{n_{1}^{\prime}(k)},{n_{N}^{\prime}(k)}} \right\rbrack} & \ldots & 1 \end{bmatrix}$

is an N×N Matrix.

The estimated error terms e_(j), can be computed as follows:

$\begin{bmatrix}  \\  \\

\end{bmatrix} = {R^{- 1} \cdot \begin{bmatrix} {{CORR}\left\lbrack {{v^{\prime}(k)},{n_{1}^{\prime}(k)}} \right\rbrack} \\ {{CORR}\left\lbrack {{v^{\prime}(k)},{n_{2}^{\prime}(k)}} \right\rbrack} \\ \vdots \\ {{CORR}\left\lbrack {{v^{\prime}(k)},{n_{N}^{\prime}(k)}} \right\rbrack} \end{bmatrix}}$

The R matrix consists of a correlation of n_(j)′(k) and n_(i)′(k) which can be computed easily. The estimated errors ê_(i) can then be calculated as:

$= {\frac{N - 1}{N} \cdot {{CORR}\left\lbrack {{v^{\prime}(k)},{n_{i}^{\prime}(k)}} \right\rbrack}}$

Once ê_(i) is estimated, the replica DAC at ADC output is populated with these estimated error values. The correction block to remove the DAC error in the replica DAC is a low rate multiply and add operation which can easily be accommodated in the subsequent digital filter chain. Because the estimation and computation operations run at a much lower rate than the modulator itself, there is a significant savings in power consumption. This solution is attractive for use in wide-band, high-speed, high performance sigma-delta modulators.

While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. 

What is claimed is:
 1. A circuit for estimating unit current element mismatch error in a digital to analog converter circuit, where unit current elements of the digital to analog converter circuit are actuated in response to bits of a thermometer coded signal generated in response to a quantization output signal, comprising: a correlation circuit configured to generate estimates of the unit current element mismatch error from a correlation of a first signal derived from the thermometer coded signal and a second signal derived from the quantization output signal.
 2. The circuit of claim 1, wherein bits of the thermometer coded signal are randomly scrambled.
 3. The circuit of claim 1, further comprising: a first signal processing circuit configured to process the thermometer coded signal to generate a signal measure that is constant and independent of the thermometer code of thermometer coded signal; a second signal processing circuit configured to filter the signal measure to generate a filtered signal measure; and a third signal processing circuit configured to filter the quantization output signal to generate a filtered quantization output signal; wherein the correlation circuit functions to correlate the filtered signal measure and the filtered quantization output signal to generate the estimates of the unit current element mismatch error.
 4. The circuit of claim 3, wherein the filtering by the second signal processing circuit is high pass filtering.
 5. The circuit of claim 3, wherein the filtering by the second signal processing circuit is combination of a high pass filtering and error transfer filtering.
 6. The circuit of claim 3, wherein the filtering by the third signal processing circuit is high pass filtering.
 7. The circuit of claim 3, wherein the first signal processing circuit comprises: a summation circuit configured to sum bits of the thermometer coded signal; a fraction circuit configured to divide the summed bits of the thermometer coded signal by a number of the bits in the thermometer coded signal to produce an output signal; and a subtraction circuit configured to generate the signal measure by subtracting the output signal from the bits of the thermometer coded signal.
 8. A system, comprising: a quantization circuit configured to generate a quantization output signal; a digital to analog converter (DAC) circuit including unit current elements that are actuated in response to bits of a thermometer coded signal generated in response to the quantization output signal; and an error estimation circuit configured to estimate unit current element mismatch error in the digital to analog converter circuit, wherein the error estimation circuit comprises: a correlation circuit configured to generate the estimates of the unit current element mismatch error from a correlation of a first signal derived from the thermometer coded signal and a second signal derived from the quantization output signal.
 9. The system of claim 8, further comprising: a replica DAC circuit that receives the quantization output signal and is configured to apply a correction for the unit current element mismatch error in response to the estimates of the unit current element mismatch error generated by the correlation circuit.
 10. The system of claim 9, wherein the quantization circuit and digital to analog converter circuit are circuit components of a sigma-delta analog to digital converter and the quantization output signal is an analog to digital converter output signal.
 11. The system of claim 10, wherein the sigma-delta analog to digital converter further comprises: a loop filter having an input configured to receive a difference signal derived from an an analog signal output from the digital to analog converter circuit and an output coupled to an input of the quantization circuit.
 12. The system of claim 10, further comprising a decimation filter having an input coupled to an output of the replica DAC circuit.
 13. The system of claim 8, further comprising a scrambling circuit configured to scramble bits of the thermometer coded signal input to the digital to analog converter.
 14. The system of claim 8, wherein the correlation circuit comprises: a first signal processing circuit configured to process the thermometer coded signal to generate a signal measure that is constant and independent of the thermometer code of thermometer coded signal; a second signal processing circuit configured to filter the signal measure to generate a filtered signal measure; and a third signal processing circuit configured to filter the quantization output signal to generate a filtered quantization output signal; wherein the correlation circuit functions to correlate the filtered signal measure and the filtered quantization output signal to generate the estimates of the unit current element mismatch error.
 15. The system of claim 14, wherein the filtering by the second signal processing circuit is high pass filtering.
 16. The system of claim 14, wherein the filtering by the second signal processing circuit is combination of a high pass filtering and error transfer filtering.
 17. The system of claim 14, wherein the filtering by the third signal processing circuit is high pass filtering.
 18. The system of claim 14, wherein the first signal processing circuit comprises: a summation circuit configured to sum bits of the thermometer coded signal; a fraction circuit configured to divide the summed bits of the thermometer coded signal by a number of the bits in the thermometer coded signal to produce an output signal; and a subtraction circuit configured to generate the signal measure by subtracting the output signal from the bits of the thermometer coded signal.
 19. A sigma-delta modulator, comprising: a differencing circuit having a first input configured to receive an input signal and a second input configured to receive a feedback signal and an output configured to generate a difference signal; a loop filter circuit configured to filter the difference signal and generate a change signal; a quantization circuit configured to sample the change signal at a sampling frequency rate, quantize the sampled change signal and generate a stream of code words; a digital-to-analog converter (DAC) circuit configured to generate the feedback signal by converting a thermometer coded signal generated in response to the stream of code words, wherein the DAC circuit has a non-ideal operation due to mismatch error; a replica DAC circuit that provides a digital replication of the DAC circuit, said digital replication comprising estimated error programming which accounts for the non-ideal operation of the DAC circuit due to mismatch error; and an error estimation circuit configured to generate the estimated error programming from a correlation of the thermometer coded signal and the stream of code words.
 20. The sigma-delta modulator of claim 19, wherein the error estimation circuit comprises: a first signal processing circuit configured to process the thermometer coded signal to generate a signal measure that is constant and independent of the thermometer code of thermometer coded signal; a second signal processing circuit configured to filter the signal measure to generate a filtered signal measure; and a third signal processing circuit configured to filter the stream of code words to generate a filtered stream of code words; wherein the correlation circuit functions to correlate the filtered signal measure and the filtered stream of code words to generate the estimated error programming.
 21. The sigma-delta modulator of claim 20, further comprising a scrambling circuit configured to scramble bits of the thermometer coded signal input to the digital to analog converter.
 22. The sigma-delta modulator of claim 20, wherein the filtering by the second signal processing circuit is high pass filtering.
 23. The sigma-delta modulator of claim 22, wherein the filtering by the second signal processing circuit is combination of a high pass filtering and error transfer filtering.
 24. The sigma-delta modulator of claim 22, wherein the filtering by the third signal processing circuit is high pass filtering.
 25. The sigma-delta modulator of claim 22, wherein the first signal processing circuit comprises: a summation circuit configured to sum bits of the thermometer coded signal; a fraction circuit configured to divide the summed bits of the thermometer coded signal by a number of the bits in the thermometer coded signal to produce an output signal; and a subtraction circuit configured to generate the signal measure by subtracting the output signal from the bits of the thermometer coded signal.
 26. The sigma-delta modulator of claim 19, further comprising a decimation filter having an input coupled to an output of the replica DAC circuit. 